A memory controller is incorporated in an arithmetic processing device (CPU chip) and controls memory access to a main memory in response to a memory access request from an arithmetic processor core (CPU core). Alternatively, the memory controller is provided between the arithmetic processing device (CPU chip) and main memory and controls memory access from the arithmetic processing device.
A double data rate (DDR) synchronous dynamic random access memory (SDRAM) has been widely used as the main memory. The DDR SDRAM receives a clock from a memory controller and returns a data strobe signal (referred to hereinbelow as “DQS signal”) generated on the basis of the clock and a data signal (referred to hereinbelow as “DQ signal”) synchronized with the rising edge and falling edge of the DQS signal to the memory controller. The memory controller also detects the H level or L level of the DQ signal by using the timing of the rising edge and falling edge of the DQS signal.
According to the DDR standard, the DQS signal is a differential signal with a duty ratio of 50% and the DQ signal is a single-phase signal, and the SDRAM transmits those signals to the memory controller. In response, the memory controller detects the phases of the rising edge and falling edge of the received DQS signal, generates the internal DQS signal, and latches the DQ signal on the basis of the timing of the internal DQS signal. The memory controller also has an input buffer that compares the received DQ signal with a reference voltage and generates an H-level or L-level internal DQ signal.
The memory controller is disclosed in WO 2011/077573, JP07-312538, JP10-145222 and JP2010-282684.